In integrated circuits, a vertical electrical contact is established between conductor tracks of different metallization levels by using so-called vias. Vias, i.e. trenches orientated vertically with respect to a substrate surface, are frequently created by using a lithography and a plasma etching method and can then be filled with electrically conductive material. Between the material of a conductor track of a metallization level to be contacted, and the material of a via, an adhesive, barrier or seed layer (liner layer) can be provided by means of which a contact can be established between the two materials to be coupled or an unwanted diffusion of material of the via filling into that of the conductor track (or vice versa) can be prevented.
Due to process-related fluctuations in the adjustment of etching masks for vias, however, these cannot be patterned optimally but only with a certain, for example lateral offset. Such an offset lies within the limits specified in design rules for designing an integrated circuit, but cannot be precisely determined for an individual via. Such fluctuations are taken into consideration in the design rules for designing the integrated circuit by means of rules which, for example, define greater than nominally required contact areas for vias in order to ensure later contact between conductor track and the via filled with electrically conductive material.
Apart from the area of the via itself, the layout takes into consideration larger metal areas on which the vias land, including the adjustment error described. This is not a weakness of the process but is necessitated by the processing. For all production steps, a tolerance range must be defined within which a physical quantity has to lie in order to be able to correctly deliver the microelectronic component to be produced.
The larger areas are called “landing pads” for vias and must be taken into consideration in the design rules for forming an integrated circuit. For example, a via bottom can have a diameter of 200 nm. Such a via must be positioned, for example, on an area of 240 nm×240 nm (edge length). In this case, a maximum offset of 20 nm per edge would be permissible.
The larger areas lead to a lateral winding of the metal tracks in the environment of the vias which interrupts the routing in the design. This is disadvantageous with regard to the high costs of chip area since it increases the space required for an integrated circuit. Metal tracks themselves can be processed at a small distance from one another but the vias require widening of the metal track for forming the landing pads. This additional expenditure in the layout and the associated loss in chip area is disadvantageous with regard to the requirement for ICs with increasingly greater integration.
As the dimensions of ICs and their components such as conductor tracks shrink further, as has to be expected, the cases shown, in particular, in FIG. 1A to FIG. 1C, can occur.
FIG. 1A shows a layout top view 110 with a conductor track 100 which is to be contacted by means of a via 101. The diameter of the via 101 is greater than the width of the conductor 100 so that, in the case of a process-related lateral offset between the centroids of the conductor track 100 and the via 101, contacting of the conductor track 100 by the via 101 must still be guaranteed.
In a second layout top view 120, which is shown in FIG. 1B, the diameter of a via 101 and of a conductor track 100 are of the same size but, due to an edge position error in the via exposure, the via 101 is partially arranged adjacently to the conductor track 100 which can lead to a poorer electrical contacting.
In a third layout top view 130 shown in FIG. 1C, a conductor track 100 and a via 101 is again shown where the via 101, in spite of local track widening in form of a landing pad 102, comes to lie adjacently to the conductor track 100 due to the adjustment tolerance of the phototechnology during the formation of the via 101.
In the further text, a method for manufacturing a layer arrangement according to the prior art, by means of which an integrated circuit according to the first layout top view 110 from FIG. 1A can be formed, referring to FIG. 2A to FIG. 2H.
To obtain the layer sequence 200 shown in FIG. 2A, an aluminum layer 201 is applied to a substrate (not shown) and, depending on the intended fineness of pattern, an additional ARC (antireflective coating) layer. On the aluminum layer 201, photoresist material is subsequently formed which is patterned to form a photoresist mask 202, using a lithography method and an etching method.
To obtain the layer sequence 210 shown in FIG. 2B, the aluminum layer 201, starting with the layer sequence 200 shown in FIG. 2A and using the photoresist mask 202, is patterned in such a way that aluminum conductor tracks 211 are formed. Depending on the intended fineness of pattern, a hard-surface mask can be used for patterning the aluminum conductor tracks 211. The photoresist 202 is then removed already after the pattern has been transferred into the hard-surface mask. The hard-surface mask then replaces the photoresist mask 202. On each of the aluminum conductor tracks 211, a photoresist residue 212 remaining after the etching is shown which is subsequently removed by means of a stripping method.
To obtain the layer sequence 220 shown in FIG. 2C, starting from the layer sequence 210 shown in FIG. 2B and after removal of the photoresist residue 212, a silicon oxide layer 221 is deposited which covers the aluminum conductor tracks 211.
To obtain the layer sequence 230 shown in FIG. 2D, photoresist material is deposited on the layer sequence 220 and patterned, by using a lithography method and an etching method, to form a photoresist mask 231.
To obtain the layer sequence 240 shown in FIG. 2E, the layer sequence 230, using the photoresist mask 231 as etching mask, is subjected to an etching method as a result of which material of the silicon oxide layer 221 is removed and trenches 242 are formed. Residue photoresist areas 241 remain on the surface of the layer sequence 240.
The layer sequence 250 shown in FIG. 2F is obtained when, starting from the layer sequence 240, the method for etching the silicon oxide layer 221 is continued. At a certain process time during this etching method, the depth of the trenches 242 is such that surface areas of the aluminum conductor tracks 211 are exposed. The layer sequence 250 according to this process state is shown in FIG. 2F where the via etching has already arrived on the patterned metal track 211.
To obtain the layer sequence 260 shown in FIG. 2G, the etching method described with reference to FIG. 2E and FIG. 2F is continued. Due to process-related differences in thickness, frequently occurring in practice, of the patterned silicon oxide layer (as interlayer dielectric, ILD) above a wafer as substrate, overetching is required, i.e. deeper etching than to the surface areas of the conductor tracks 221. This overetching is performed so that the vias can later can be reliably connected to conductor tracks 211 on the wafer. The duration of overetching is typically 10% to 30% of the entire via etching time. The result of the overetching process is shown in layer sequence 260. Although the surface areas of the conductor tracks 211 are reliably exposed, enabling contacting with via material in a subsequent process step, narrow gaps 261 form in the boundary areas between material of the silicon oxide layer 221 and the exposed sections of the conductor tracks 211 due to the overetching, as shown in FIG. 2G.
As a result of the overetching, the etching thus bypasses the metal tracks 211 on both sides and creates narrow gaps 261. The depth of the gaps 261 and thus their aspect ratio depend on the local thickness of the dielectric layer 211 and can vary across the wafer. These narrow gaps 261 are the cause of many problems which lead to severe reliability problems. Thus, polymer material in the gaps 261 can only be cleaned or removed incompletely or not at all. This leads to problems in a subsequent liner deposition and/or metal filling for forming the vias. Furthermore, adhesive, seed or barrier layers, called liners, can only be deposited incompletely when narrow gaps 261 occur. Since, as a rule, such a depositing occurs by using also physical processes, the locally existing aspect ratio of the narrow gaps 261 plays an important role. The higher the aspect ratio, the smaller the edge covering with the respective layer. During the metal filling, cavities can thus arise in the area of the narrow gaps 261 or individual vias are not filled at all or only badly. This leads to unreliable contacting between metal tracks 211 and vias.
To obtain the layer arrangement 270 according to the prior art, shown in FIG. 2H, the trenches 242 from FIG. 2G are filled with tungsten material for forming tungsten vias 271. As described above, the narrow gaps 261 with locally greatly increased aspect ratio, formed due to the overetching, cannot be filled up reliably. This leads to problems with regard to the quality of the layer arrangement 270 with regard to its use as integrated circuit.
In the further text, it is again described, referring to FIG. 2I to FIG. 2K, what processes lead to the formation of the unwanted narrow gaps 261 when the process for producing a layer arrangement according to FIG. 2A to FIG. 2H is carried out.
The layer sequence 280 shown in FIG. 2I shows a state during the etching of the silicon oxide layer 221 in which the etch front has reached a first level 282.
As shown in FIG. 2J, a layer sequence 285 is obtained when, starting from the layer sequence 280, the etching process for etching the first silicon oxide layer 221 is continued. The etch front then extends up to a second level 283.
Since a certain overetching is required for ensuring that all surfaces of all aluminum conductor tracks 211 are exposed is technologically required, the case shown in FIG. 2K in which the etch front has penetrated to a third level 284 in a layer sequence 290 occurs according to the prior art, so that unwanted narrow gaps 261 occur at lateral areas of the exposed aluminum conductor track 211.
For the cases shown in FIG. 1B and FIG. 1C, a similar picture is obtained as for FIG. 1A. There is always deep etching-in next to the metal track which then leads to the problems described above.